Hybrid Vs Memory-to-memory Communication in Multi-core Processor

Now a day’s multi-core architecture introduces new challenges for effective implementation of inter-core communication, as Inter-core communication plays an important role to balance the delay in a multicore processor. The two mechanisms used for inter-core communication are sharedmemory and message-passing communications. Shared-memory communication fails to provide sufficient scalability with the increasing number of processor, where as message-passing communication though have high scalability, but it doesn’t have guaranteed Quality-ofservice (QoS). To overcome the above drawbacks a combined mechanism named Hybrid inter-core communication [1] is prevalent to till date. Recently we proposed a new technique named Memory-to-Memory communication which provides the direct memory to memory communication by using DMA as memory interface [2]. This paper mainly concentrates on comparing our proposed method with the existing methods till date, with respect to delay. All the intercore communication system mechanisms have been designed in 90nm CMOS using XILINX 12.2 version platform. Comparing the performance of all communication systems it is observed that the communication time is least for Memory-to-Memory communication. Key words—Chip multiprocessor, Direct Memory Access, hybrid inter-core communication, inter-core communication, shared-memory, multi-core, message-passing, network-on-chip (NoC), inter-core synchronization, Memory to Memory.